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NCV8512 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Monitor FLAG
The NCV8512 is a 5.0 V precision micropower voltage regulator. The output current capability is 150 mA. The output voltage is accurate within 2.0% with a maximum dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 130 mA with a 100 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY), and a FLAG monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the FLAG monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.
Features http://onsemi.com MARKING DIAGRAM
16 1 SOIC 16 LEAD WIDE BODY EXPOSED PAD PW SUFFIX CASE 751AG NCV8512 AWLYYWWG
16
1
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Device
PIN CONNECTIONS*
NC VOUT NC NC NC NC VIN MON 1 16 FLAG RESET NC GND NC NC DELAY RADJ
* * * * * *
* * *
5.0 V 2.0% Output Low 130 mA Quiescent Current Active RESET Adjustable Reset 150 mA Output Current Capability Fault Protection - +60 V Peak Transient Voltage - -15 V Reverse Voltage - Short Circuit - Thermal Overload Early Warning through FLAG/MON Leads Thermally Enhanced in SOW-16 Exposed Pad NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
*Pin connections for reference only.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
December, 2006 - Rev. 0
Publication Order Number: NCV8512/D
NCV8512
VBAT 10 mF NCV8512 Delay CDELAY
VIN
VOUT RADJ1 RADJ RM1 RFLG 10 k RRST 10 k RADJ2 10 mF
VDD
MON RM2
FLAG GND
RESET
I/O
I/O
Figure 1. Application Diagram
MAXIMUM RATINGS
Rating VIN (DC) Peak Transient Voltage (46 V Load Dump @ VIN = 14 V). Voltage with respect to ground. Operating Voltage VOUT (DC) Voltage Range (RESET, FLAG) Input Voltage Range (MON) VDELAY VRADJ ESD Susceptibility (Human Body Model) Junction Temperature, TJ Storage Temperature, TS Package Thermal Resistance, SOW-16 E Pad: Junction-to-Case, RqJC Junction-to-Ambient, RqJA Lead Temperature Soldering: Moisture Sensitivity Level at 260C Reflow: (SMD styles only) (Notes 1, 2. and 3) Value -15 to 45 60 45 16 -0.3 to 10 -0.3 to 10 -0.3 to 4.0 -0.3 to 10 2.0 -40 to +150 -55 to 150 16 57 265 peak 1 C Unit V V V V V V V V kV C C C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. 1. 60 second maximum above 217C. 2. -5C/+0C allowable conditions. 3. Per IPC/JEDEC J-STD-020C.
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Microprocessor
NCV8512
ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, -40C TJ 125C; 6.0 V < VIN < 26 V; unless otherwise specified.)
Characteristic OUTPUT STAGE Output Voltage 9.0 V < VIN < 16 V, 100 mA IOUT 150 mA 6.0 V < VIN < 26 V, 100 mA IOUT 150 mA IOUT = 150 mA IOUT = 1.0 mA VIN = 14 V, 5.0 mA IOUT 150 mA [VOUT(typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA IOUT = 100 mA, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V IOUT = 75 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V IOUT 150 mA, VIN = 14 V, Delay = 3.0 V, MON = 3.0 V - VOUT = 0 V (Guaranteed by Design) 4.90 4.85 - - -30 - - - - 151 40 150 5.0 5.0 400 100 5.0 15 130 4.0 12 300 190 180 5.10 5.15 600 150 30 60 200 6.0 19 - - - V V mV mV mV mV mA mA mA mA mA C Test Conditions Min Typ Max Unit
Dropout Voltage (VIN - VOUT) Load Regulation Line Regulation Quiescent Current, (IQ) Active Mode
Current Limit Short Circuit Output Current Thermal Shutdown RESET FUNCTION (RESET) RESET Threshold HIGH (VRH) LOW (VRL) Output Voltage Low (VRLO) Delay Switching Threshold (VDT) Lower Delay Switching Threshold (VLD) Reset Delay Low Voltage Delay Charge Current Delay Discharge Current Reset Adjust Switching Voltage (VR(ADJ)) FLAG/MONITOR Monitor Threshold Hysteresis Input Current Output Saturation Voltage MON = 2.0 V
VOUT Increasing VOUT Decreasing 1.0 V VOUT VRL, RRESET = 10 k - -
4.55 4.50
4.70 4.60
0.98 x VOUT 0.97 x VOUT
V V
- 1.4 0.3
0.1 1.8 0.45
0.4 2.2 0.6
V V V
VOUT < RESET Threshold Low(min) DELAY = 1.0 V, VOUT > VRH DELAY = 1.0 V, VOUT = 1.5 V -
- 6.0 5.0 1.23
- 9.0 - 1.31
0.1 15 - 1.39
V mA mA V
Increasing and Decreasing -
1.10 20 -0.5 -
1.20 50 0.1 0.1
1.31 100 0.5 0.4
V mV mA V
MON = 0 V, IFLAG = 1.0 mA
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NCV8512
PACKAGE PIN DESCRIPTION
Package Pin Number SOW-16 Exposed Pad 1, 3-6, 11, 12, 14 2 7 8 9 10 13 15 16 Pin Symbol NC VOUT VIN MON RADJ DELAY GND RESET FLAG No connection. 2.0%, 150 mA output. Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. Reset Adjust. If not needed connect to ground. Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT 1.0 V). Open collector output from early warning comparator. Function
TYPICAL PERFORMANCE CHARACTERISTICS
5.01 VOUT = 5.0 V VIN = 14 V IOUT = 5.0 mA 5.00 VOUT (V) IQ (mA) 1.2 VIN = 12 V 1.0 0.8 0.6 0.4 0.2 4.98 -40 -25 -10 0 +125C +25C -40C
4.99
5
20 35 50 65 Temperature (C)
80
95 110 125
0
5
10 15 IOUT (mA)
20
25
Figure 2. Output Voltage vs. Temperature
Figure 3. Quiescent Current vs. Output Current
14 VIN = 12 V 12 10 IQ (mA) 8 6 -40C 4 2 0 0 15 30 45 60 75 90 IOUT (mA) 105 120 135 140
7 T = 25C 6 5 IQ (mA) 4 3 2 1 0 6 8 10 12 14 IOUT = 50 mA IOUT = 100 mA
+125C +25C
IOUT = 10 mA 16 18 VIN (V) 20 22 24 26
Figure 4. Quiescent Current vs. Output Current
Figure 5. Quiescent Current vs. Input Voltage
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NCV8512
TYPICAL PERFORMANCE CHARACTERISTICS
150 IOUT = 100 mA 145 140 IQ (mA) T = 25C 135 130 125 120 Dropout Voltage (mV) 450 400 350 300 +125C 250 200 150 100 50 6 10 14 VIN (V) 18 22 26 0 0 25 50 75 IOUT (mA) 100 125 150 +25C -40C
Figure 6. Quiescent Current vs. Input Voltage
Figure 7. Dropout Voltage vs. Output Current
1000 Unstable Region
1000 Unstable Region 100 CVOUT = 10 mF CVOUT = 0.1 mF ESR (W) 10
100 ESR (W)
10 Stable Region
1 Stable Region 0.1
CVOUT = 10 mF 1 0 10 20 30 40 50 60 70 80 90 100 110120130140150 OUTPUT CURRENT (mA) 0.01
0 10 20 30 40 50 60 70 80 90 100 110
OUTPUT CURRENT (mA)
Figure 8. Output Capacitor ESR
Figure 9. Output Stability with Output Capacitor Change
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NCV8512
VOUT Current Source (Circuit Bias) IBIAS Current Limit Sense
VIN
RADJ VBG RESET
+ + -
IBIAS +- Error Amplifier + - 1.8 V Thermal Protection VBG
3.0 mA Delay IBIAS
Bandgap Reference VBG +
VBG
GND
IBIAS FLAG
MON
-
Figure 10. Block Diagram
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NCV8512
CIRCUIT DESCRIPTION
VIN
VOUT
RESET Threshold
DELAY
1.8V VDT 0.45V VLD
RESET Td Power on Reset Input Under-voltage V Dip Td Secondary Output Spike Overload
Figure 11. Reset and Delay Circuit Wave Forms
REGULATOR CONTROL FUNCTIONS The NCV8512 contains a microprocessor-compatible control function RESET (Figure 11).
RESET Function
A RESET signal (low voltage) is generated as the IC powers up. After VOUT increases above the RESET threshold, the DELAY timer is started. When the DELAY timer passes 1.8 V, the RESET signal goes high. A discharge of the DELAY timer is started when VOUT drops and stays below the RESET threshold. When the DELAY timer level drops below 0.45 V, the RESET signal is brought low. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.
Adjustable Reset Function
If the reset adjust option is not needed, the RADJ pin should be connected to GND causing the reset threshold to go to its default value (4.65 V typical). As an example, select resistors to give a threshold voltage of 4.0 V. This will allow the delay timer to start when the output crosses the 4.0 V level. VTHRES = 4.0 V = 1.31 V x (RADJ1 + RADJ2) / RADJ2 Let RADJ2 be 100 kW for low current consumption. RADJ1 = 2.05 x 100 k = 205 kW With 5 V on the output, the voltage on the RADJ pin will be 1.64 V.
RADJ1 RADJ RADJ2 VOUT RRST to mP and System Power
NCV8512
COUT
The reset threshold VRL can be decreased from a typical value of 4.65 V to as low as 3.5 V by using an external voltage divider connected from VOUT to the pin RADJ as displayed in Figure 12. The resistor divider keeps the voltage above the VRADJ.TH (typical 1.31 V) and overrides the internal threshold detector. Adjust the voltage divider according to the following relationship:
VTHRES + VRADJ.TH RADJ1 ) RADJ2 RADJ2
(2)
Delay
RESET
CDELAY 6.4 V
to mP and RESET Port
Figure 12. Adjustable RESET DELAY Function
Where; VTHRES is the desired output threshold voltage that starts the time delay for Power on Reset Delay. VRADJ.TH is the default threshold voltage of 1.31 V typ. RADJ1 is the resistor connected from the 5 V output to the RADJ pin. RADJ2 is the resistor connected from the RADJ pin to ground.
The reset delay circuit provides a delay (programmable by external capacitor) on the RESET output lead. The DELAY lead provides source current (typically 9 mA) to the external DELAY capacitor at the following times: 1. During Power Up (once the regulation threshold has been exceeded).
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NCV8512
2. After a reset event has occurred and the device is back in regulation. The DELAY capacitor is discharged when the regulation (RESET threshold) has been violated. When the DELAY capacitor discharges to 0.45 V, the RESET signal pulls low.
FLAG/Monitor Function
trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 13). The typical threshold is 1.20 V on the MON Pin.
VBAT VIN RM1 RM2 RADJ Delay RESET GND VOUT NCV8512 MON FLAG RRST RESET RFLG COUT I/O
VCC mP
An on-chip comparator is available to provide an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the FLAG pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap voltage. The actual
Figure 13. FLAG/Monitor Function
APPLICATION NOTES FLAG MONITOR Figure 14 shows the FLAG Monitor waveforms taken from the circuit depicted in Figure 13. As the output voltage falls (VOUT), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET shutdown signal.
VOUT
Use the typical value for VDT = 1.8 V. Use the typical value for Delay Charge Current = 9.0 mA.
tDELAY + [33 nF(1.8 * 0.04 V)] + 6.45 ms 9.0 mA
MON FLAG Monitor Ref. Voltage
RESET
FLAG
STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 15 should work for most applications, but is not necessarily the optimized solution.
VIN VOUT
TWARNING
CIN* 0.1 mF
NCV8512
RESET
RRST
Figure 14. FLAG Monitor Circuit Waveform
COUT** 10 mF
SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation:
[C (V * Reset Delay Low Voltage)] tDELAY + DELAY DT Delay Charge Current
*CIN required if regulator is located far from the power supply filter. **COUT required for stability. Capacitor must operate at minimum temperature expected.
Example: Using CDELAY = 33 nF. Use the typical value for Delay Low Voltage = 0.04 V.
Figure 15. Test and Application Circuit Showing Output Compensation
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NCV8512
CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 16) is:
PD(max) + [VIN(max) * VOUT(min)] IOUT(max) ) VIN(max)IQ
(1)
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
T RqJA + 150C * A PD
(2)
HEATSINKS A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(3)
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
IIN VIN SMART REGULATOR(R) IOUT VOUT
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heat sink manufacturers. Further mounting and cooling information is available in the application note, AN1040/D, "Mounting Considerations for Power Semiconductors" located in the ON Semiconductor web site.
} Control Features
IQ
Figure 16. Single Output Regulator with Key Performance Parameters Labeled
ORDERING INFORMATION
Device NCV8512PW50G 5.0 V NCV8512PW50R2G Output Voltage Package SOW-16 E Pad (Pb-Free) Shipping 47 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCV8512
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD PW SUFFIX CASE 751AG-01 ISSUE O
-U- A M
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. DIM A B C D F G H J K L M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.31 3.51 0.25 0.32 0.00 0.10 4.58 4.78 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.130 0.138 0.010 0.012 0.000 0.004 0.180 0.188 0_ 7_ 0.395 0.415 0.010 0.029
P 0.25 (0.010)
M
W
M
1 8
B R x 45_ -W-
PIN 1 I.D.
G TOP SIDE
14 PL
DETAIL E
C -T- 0.10 (0.004) T D 16 PL 0.25 (0.010) H
M
F
K TU
S
SEATING PLANE
W
S
J DETAIL E
SOLDERING FOOTPRINT*
EXPOSED PAD 1 8
0.350 L 0.175 0.050
Exposed Pad
16
9
BACK SIDE
C L 0.200 0.074
0.188 C L 0.376
0.024
0.145
DIMENSIONS: INCHES
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NCV8512/D

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